Existing computing platforms may host multiple partitions to simultaneously carry out multiple tasks. Computation time of a processor may be made available to one or more Hosted Function (HF)s by activating each partition for a period of time using a predicable schedule. This may allow each HF to enjoy and expect a provisioned portion of the computation time of the processor.
Existing avionics Integrated Modular Avionics (IMA) computing platforms may also use this partitioning scheme to carry out avionics related functions. IMA computing platforms may have various processor types including a single core processor as well as a multiple core processor. As IMA computing platforms and numbers of cores advances with computational requirements, computational partitioning and available cache may increase in desirability to the corresponding increase in HF number and complexity.
In avionics, a large portion of processor time may be expended accessing memory normally via three operations (data read, data write, and instruction read). Very few avionics HFs retain algorithmic logic code and computation data in processor cache, and spend the activated processor time refining the computation on this data. Instead, most avionics HF 1) gather large amounts of data, 2) compute on the data using large portions of algorithmic code (large relative to the cache size), and 3) produce large amounts of computed data for avionics use.
The time needed for an avionics HF to access memory is a significant contributor to the computation ability available in a fixed period of time. Some processor designs may include a processor cache associated with the core processor in order to expedite a mean rate of cache memory access. The time needed to access data available in the cache memory may be significantly less than the time needed for the HF to access the physical memory.
During the activation time of a HF, the HF interacts with the cache and writes data content to the cache. During this time of HF execution a portion of the data content in the cache that will be needed for future cache accesses by that HF increases. This is due to 1) cache size capacity holding previous data access, 2) cache architecture using multiple ways, and 3) the use of spatial or temporal look-ahead policies. When a first HF is paused and additional HFs are allowed to run, the cache content begins to reflect the accesses of the additional HFs. The cache content that will be needed by the paused first HF is slowly overwritten as the additional HFs run.
Each avionics processing system may be required to be certified before being installed and used within the avionics suite of an aircraft. Rigorous testing and certification performance standards may be imposed by a certification authority before a system may become certified. A minimum performance requirement may be required of a HF before certification is awarded.
When using an IMA partitioned HF schedule, HFs may be activated and deactivated based on the schedule. In certification of an IMA partitioning strategy, one concern may include the predictability of the cache content state when a HF is activated. The amount of time needed for a HF to perform its intended function is directly influenced by the state of the cache content upon HF activation.
One concern in certification may include if the cache state were left unknown, then perhaps at activation of the first HF, the cache state may or may not be sufficient to allow the first HF to complete its intended operation.
One traditional method of mitigating an unknown cache state when activating a HF may include a system designed to invalidate or ‘flush’ all of the cache prior to the first HF activation. This may ensure that all accesses that occur during the activation period of the HF will be influenced only by the sequence of accesses made following the time of activation. Therefore, the computation performance is deemed deterministic in the sense that it is known similar results will be found in operation as well as during a controlled certification. This traditional strategy may provide a straightforward certification method—as the cache state is known, each time the first HF is activated, the first HF may always find a guaranteed amount of available cache to properly operate.
Another traditional method of cache management may include a cast out policy applied to the cache. A traditional cast out policy may choose what contents of cache are removed at the deactivation point of a HF and replaced with new data stored in the cache. Because computational capacity is strongly dependent on the rate at which a processor may be able to read the cache, the cast out policy may directly affect the state of the cache therefore directly impacting the HF success at activation.
The problems with these traditional methods may include 1) the time to perform cache invalidation or operate a cast out policy may be large (this is often not considered, but the invalidation time can be long and variable in duration), 2) time to perform a cache invalidation may can be unpredictable as it is dependent on the cache state residue from previous activated HFs, 3) scalability—time for a invalidation and cast out of a large cache may be large enough to affect the activation scheduling policy, and 4) only some or no relevant content remains—cache state is fully cleared (this makes the activated HF less efficient than it would be if some valid cache remained).
Therefore, as traditional methods are unpredictable, take time and processor power, and ultimately make each HF less efficient, a need remains for method and system capable of cache retention to enable a desired HF quick access to desirable cache for immediate HF activation and operation.